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| Vorlesung WS11/12 (2 + 2 h) |
(Prof. Dr. Ulrich Brüning)
| Lecture - Vorlesung |
Do wtl; 20.10.2011 - 02.02.2012: 9.15-11.15; Ort: MA B 6,26, A3.04;
Content:
Introduction to the Principles of Hardware design. The main focus is on the use of Hardware Description Languages like Verilog HDL. Step by step, the design of combinational and sequential logic is presented. And the overall design flow for Integrated Circuits (IC) is discussed.
Script:
During the semester a script will be available on the Elearning platform.
| Exercises - Übung |
Do wtl: 20.10.2011 - 02.02.2012: 13.45-15.15; Ort: B 6,26, B3.15
Exercises:
During the semester exercises will be available on the Elearning platform.
| Useful links about hardware design |
- Rajesh Bawankule's Verilog Center
- Here you'll find a lot of Verilog stuff: FAQ, free tools, more links etc.
- Verilog Quick Reference
- A nice online Verilog quick ref by Sutherland HDL Inc.
Last modified: 21.10.2011
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WS 11/12Functional Verification
High Performance Interconnects
Entrepreneurship
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Contact
Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: ulrich.bruening {at} ziti.uni-heidelberg.de
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68131 Mannheim
Fon: +49 (0) 621 - 181 2723
Fax: +49 (0) 621 - 181 2713
Email: ulrich.bruening {at} ziti.uni-heidelberg.de
Delivery Address
Universität Heidelberg
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68159 Mannheim
LS Rechnerarchitektur
Prof. Dr. U. Brüning
B6, 26, Building B (3rd floor)
68159 Mannheim
HT Center of Excellence
